A Low Power High Accuracy Cmos Time-to-digital Converter

actly in the last delay element. In the measurement, the input period T,,, with TIl<Tref will be fed into the delay In this paper, we present a new CMOS time-toline instead. Suppose that T,, disappears in the n-th delay digital converter (TDC) with the cyclic delay line strucelement, then the width is measured as n x TrCf / N , ture. The static supply current is 2-nA only. Furthermore, where N i:s the number of elements in the delay line. For the continuous calibration is no longer needed. The TDC a 20 M H ~ reference clock and a delav line of 64 can be shunt down between measurements to make the power consumption negligible. The circuit with 64-stage cyclic delay line has been fitted into 0.25" x 0.75" chip area with a typical 0.8-pn SPDM process. The measured resolution is 286 picoseconds, and the measured single-shot accuracy is less than 143 picoseconds. Both can be made much less if the control voltage is well tuned.